This invention relates to methods of depositing polysilicon, to methods of fabricating field effect transistor, to methods of forming contacts to substrates and to methods of forming capacitors.
Device geometry continues to shrink in semiconductor circuitry fabrication. For example, field effect transistor gate width is now commonly below one micron and source/drain junction depth 1000 Angstroms or less. A challenge in such constructions is to reduce parasitic source/drain serial resistance while maintaining low source/drain diode leakage. Such resistance can be reduced by providing a thicker silicide over the source/drain. Such is typically provided by depositing a metal layer on the source/drain which typically comprises monocrystalline silicon. A subsequent anneal causes a reaction which consumes a portion of the silicon to form the silicide. However, large consumption of silicon to form the desired thicker silicide results in the silicide/junction interface being very close to the base of the junction. This causes source/drain diode leakage current to the substrate to increase.
Raised or elevated source/drain constructions in field effect transistors can be utilized to minimize or reduce the amount of silicon consumed in forming a silicide portion of a substrate contact. Further, raised source/drain constructions can provide desired field effect transistor constructions independent of the silicide contact which is typically formed. For example, raised source/drain transistors are commonly uses in logic device applications where device speed is an important factor.
Elevated source/drain constructions are typically formed in the prior art by selectively growing epitaxial monocrystalline silicon atop the silicon junction regions. Such is typically accomplished in costly epitaxial reactors operating under ultra high vacuum (UHV), for example at vacuum pressures of the order of 0.001 mTorr. Violette et al., xe2x80x9cLow temperature selective silicon epitaxy by ultra high vacuum rapid thermal chemical vapor deposition using Si2H6, H2 and Cl2xe2x80x9d, Applied Physics Letter 68(1), pp.66-68, Jan. 1, 1996 disclose a selective epi silicon deposition process occurring at 800xc2x0 C. and 30 mTorr or less.
It would be desirable to improve upon these and other prior art processes of selectively forming silicon over silicon substrates. Although motivated from this objective, the artisan will appreciate other applicability of the disclosed technology, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine Of Equivalents.
In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the crystalline region and not the amorphous region.
In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. Doped source/drain regions are formed within semiconductive material laterally proximate the gate. Substantially amorphous insulating material is formed over and laterally proximate the gate. The substrate is provided within a chemical vapor deposition reactor. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the source/drain regions and not on substantially amorphous material, and forming elevated source/drains on the doped source/drain regions.
In but another aspect, a method of forming a contact to a substrate comprises forming substantially amorphous insulating material over a substrate node location. A contact opening is etched through the amorphous insulating material over the node location. The node location is provided to comprise an outwardly exposed substantially crystalline surface. The substrate with outwardly exposed substantially crystalline node location surface is provided within a chemical vapor deposition reactor. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the outwardly exposed crystalline node location surface and not on the insulating material.
An aspect of the invention also comprises forming a capacitor. In one implementation, a substrate is provided within a chemical vapor deposition reactor. The substrate has an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the crystalline region and not the amorphous region, and the polysilicon is formed into a first capacitor electrode. A capacitor dielectric layer is formed over the polysilicon. A second capacitor electrode is formed over the capacitor dielectric layer.